Silicon Physical Design Engineer IV (39708-1)

Silicon Physical Design Engineer IV (39708-1)

Job Title: Silicon DV Engineer V (40152-1)Type: W2 ContractDuration: 12 months with scope for extension/conversionClient: Leading Social Media Company**Must have US Work Authorization**Location: Sunnyvale, CA / Redmond, WA / Austin, TXAs a custom IC Layout Design Engineer you will work with a world-class group of engineers creating high performance and area/power efficient design for our next generation AR chips and systems. You will work closely with layout, circuit, and automation teams to layout custom cells for advanced integrated circuits.Responsibilities:Read and understand circuit schematics and design specifications.Ensure that layouts meet required specifications.Layout activity will include exploratory development and evaluation in an R&D environmentPerform initial block floor planning, develop layout schedule, monitor progress, resolve issues and report status.Communicate with other layout engineers in multiple sites to identify layout best practices, methodology advances and track updates in the field to improve quality and efficiencyMinimum Qualifications:Expertise in an advanced node layout (e.g. 7nm, 5nm, 4nm, or 3nm)Ability to run DRC, LVS, EM and other physical verifications flows, interpret reports and correct layoutsExpertise with standard cell or memory layout stylesPreferred Qualifications:Experience running and modifying SKILL, Perl, Python, or Shell ScriptsExperience triaging layout and physical verification tool bugs and validating correctness of new methodologies, tool versions and foundry collaterals.

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