Silicon DV Engineer V 39437-1

Silicon DV Engineer V 39437-1

Job Title: Silicon DV Engineer V 39437-1Duration: 12 Months with possible extension or conversionJob Type: W2Location: Sunnyvale, CAJob Description: What are the top non-negotiable skill sets required for this role?• Strong DV background (test plan development, test writing, SystemVerilog, UVM)Duties:• Write and augment existing testplans.• Implement testbench and scoreboards / checkers.• Implement test sequences as per plan and debug failures• Achieve 100% functional, code, and power coverage• Work closely with designers, micro architects & f/w to resolve issues• Ability to communicate & articulate clearly progress / issues with project leadsSkills• 7+ years of proven experience as a DV engineero Implied: Candidate will have hands on Experience with executable test plans and Coverage Driven verification• Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)• Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools• Experience with UPF based simulation flow• 2+ Years of experience with C/C++Wish List/ Nice to Have:• Power and performance FPGA validation• Experience with Power Aware GLS flow• Tcl and Python (or similar) scripting language• ASIC design experience• Experience with complex SoCs• MSEE/CS or equivalent experienceEducation• Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science• Master’s Degree preferred but not required

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