Silicon DV Engineer V (38416-1)

Silicon DV Engineer V (38416-1)

Job Title: Silicon DV Engineer V (38416-1)Duration: 12 Months with scope of extensionLocation: US – CA – Other – Remote,Client : Social Media GiantApproved Remote Locations: Denver, CO , New York, NY Houston, TX , Los Angeles, CA and San Diego, CA What are the top non-negotiable skill sets required for this role?* Proficient in SystemVerilog, C/C++)* Proficient in scripting (Python or Perl)* Strong DV background (test writing, methodology, debug)Duties:* Achieve 100% functional and code coverage through analysis, test writing, and exclusions* Automate code generation for testbench using scripts* Monitor, delegate, and debug nightly test regression failures* Functional verification and performance validation of performance-related design areas* Support integration of IP block tests into larger SubSystem or SoC environment tests* Implement and maintain testbench and scoreboards / checkers.* Implement test sequences as per plan and debug failuresMust Have:* 7+ years of proven experience as a DV engineer* Hands on experience with executable test plans and coverage driven verification* Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology or equivalent)* Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools* 2+ Years of experience with C/C++* 4+ Years of experience with a scripting language (Python or Perl)Wish List/ Nice to Have:* Experience in GPU, Display, or Imaging Pipeline Silicon development.* Experience in development System Verilog UVM testbench environment from scratch* Experience with Software/Hardware Co-simulation (DPI/VPI)* Experience with C/C++ modeling of the Hardware Systems* Experience with verification of high speed interfaces like MIPI* Experience with on-chip bus protocols (AXI, AXI-Lite, AHB, OCP)* Experience with post-silicon lab/bench test/validation* Experience with UPF based simulation flowEducation* Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science* Master’s Degree preferred but not required

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