Silicon DV Engineer III (33847-1)

Silicon DV Engineer III (33847-1)

Job Title: Silicon DV Engineer III (33847-1) Type: W2 Contract Duration: 12 months with scope for extension/conversionClient: Leading Social Media CompanyLocation: Sunnyvale, CA**Must have US Work Authorization**What are the top non-negotiable skill sets required for this role?• Strong DV background (test plan development, test writing, UVM)• Strong Experience with Python and C/C++Duties:• Write and augment existing testplans.• Implement testbench and scoreboards / checkers• Write Python scripts for developing debugging tool• Achieve 100% functional, code• Work closely with designers, DV engineers and functional simulator• Ability to communicate & articulate clearly progress / issues with project leadsMust Have Skills:• 7+ years of proven experience as a DV or Infra engineer• Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)• Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools• 2+ Years of experience with Python and C/C++Wish List/ Nice to Have:• Tcl and Python (or similar) scripting language• ASIC design experience• Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators• Experience with complex SoCs• Knowledge of coverage merging across simulation and formal• MSEE/CS or equivalent experienceEducation• Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science• Master’s Degree preferred but not required

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