Silicon DV Engineer III (33808-1)

Silicon DV Engineer III (33808-1)

Job Title:Silicon DV Engineer III (33808-1)Duration: 12 months with scope of extensionlocation : Redmond WA (Remote)Client: Social Media Giant, Job Type:W2What are the top non-negotiable skill sets required for this role?• Verilog, SystemVerilog• UVM• Strong Design Verification background (test plan development, test writing)• Constrained random, Functional Coverage development, design debug experienceDuties:• Design and implement Constraint Random test benches for modules and top levels verification• Write and augment existing test plans• Implement scalable UVM testbench including elements of SV Assertions / constraints / reference models / coverage groups / agents• Achieve 100% functional and code coverage• Develop the scripts and code necessary for proper automation• Work closely with designers, firmware, and cross-functional teams to resolve issues• Ability to communicate & articulate clearly progress / issues with project leadsMust Have:3+ years of hands on proven experience as a DV engineer with SV (SystemVerilog) and UVM (Universal Verification Methodology), Object Oriented Programming• Hands on Experience with executable test plans and Coverage Driven verification• Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive / XceliumWish List/ Nice to Have:• Hands on Experience with FPGA tools such as Xilinx Vivado• Experience with Design verification of video, graphics, or camera applications• Experience with IP or integration verification of interfaces like PCIe, DDR, AXI• UVM RAL and/or VIP development experience• C/C++• Git source code management and version control system• Python / Tcl (or similar) scripting language• RTL design experience• Formal verification• Experience with complex SoCsEducation• Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science• Preferred but not required: Master’s Degree in Electrical/Computer Engineering or Computer Science

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