Process Engineer IV – ASIC Power Engineer

Process Engineer IV – ASIC Power Engineer

Job Title: Process Engineer IV 36616-1Duration: 6 Months (W2 Possible Conversion) Location: Sunnyvale, CAASIC Power EngineerASIC Power Engineer to perform power analysis and optimizations in ASIC for Meta’s AR/VR products. Areas of interests include Graphics or Machine Learning. Primary languages are Python, tcl and System Verilog.RESPONSIBILITIESPerform RTL and netlist level Power analysisPerform post-processing and scripting on report log files for format conversion, data analysis and information extractionSetup, run, debug and analyze reports of ASIC flows (Synthesis, PD, Power, Timing)Implement some blocks at RTL and UPFAbility to document and communicate clearlyMINIMUM QUALIFICATIONS10+ Years of experience as an ASIC Power engineer, or CAD Engineer/Physical Design engineerExperience with power estimation tools and synthesis, some physical designKnowledge of power trade-offs in design and back-end implementationHands-on experience in scripting, data analysisBS in Electrical Engineering/Computer Science or equivalent experiencePREFERRED QUALIFICATIONSSynopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules)Python, Perl (or similar) scripting and data-post-processing toolsExcel (or Matlab) for model fitting, data visualization and analysisExperience in low power design, tools and methodologies including power intent UPF specificationsSilicon Power CharacterizationSome power profiling experience at IP/SoC levelThe candidate should be familiar with PrimePower/PP-RTL/PowerArtist and Python.RTL Design, Physical Design10+ years of experience Power Engineer- power estimation Scripting for the overall power flow (Python and TCL) Experience with power estimation toolsWork with XFN teamsPrime Power, Prime Power RTOPTPXFusion compilerVerdiPower masidollogyARVR devices- power is critical aspect2 rounds (Background and basic knowledge about power analysis, then scripting- coder pad test for python)

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