Low Power Design Verification Engineer

Low Power Design Verification Engineer

Job Title: Low Power Design Verification EngineerLocation: Remote workDuration: 7 months W2 contract, possible extention or conversionLeading Social Media CompanyDuties:Responsible for low power verification including both dynamic and static verificationWrite and augment existing testplans.Implement testbench and scoreboards / checkers.Implement test sequences as per plan and debug failuresAchieve 100% functional, code, and power coverageWork closely with designers, micro architects & f/w to resolve issuesAbility to communicate & articulate clearly progress / issues with project leadsSkills: Must Have:7+ years of proven experience as a DV engineerImplied: Candidate will have hands on Experience with executable test plans and Coverage Driven verificationHands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive toolsExperience with UPF based simulation flow2+ Years of experience with C/C++Wish List/ Nice to Have:Experience with Power Aware GLS flowTcl and Python (or similar) scripting languageASIC design experienceMSEE/CS or equivalent experienceEducation:Must Have: Bachelor degree in Electrical/Computer Engineering or Computer ScienceMaster’s Degree preferred but not requiredRequired Skills: BSEEVERILOGSIMULATIONSSYSTEM VERIFICATIONOBJECT ORIENTED PROGRAMMINGAdditional Skills:APPLICATION-SPECIFIC INTEGRATED CIRCUITASICASIC DESIGNCADENCEALGORITHMSCODINGDEBUGMSEEPYTHONSCRIPTINGSYNOPSYSTCL
Posted On: Friday, July 24, 2020

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