Design Verification Engineer

Design Verification Engineer

Duties:Write and augment existing testplans.Implement testbench and scoreboards / checkers.Implement test sequences as per plan and debug failuresAchieve 100% functional and code coverageWork closely with designers, micro architects & f/w to resolve issuesAbility to communicate & articulate clearly progress / issues with project leadsSkills:5+ years of proven experience as a DV engineerHands on experience with SV and UVMHands on Experience with executable test plans and Coverage Driven verificationHands on Experience with Synopsys VCS / Verdi or Cadence Incisive toolsFamiliarity with C/C++BSEE/CS or equivalent experiencePreferred Qualifications:Python (or similar) scripting languageASIC design experienceExperience in Computer Graphics or Compression is desirableMSEE/CS or equivalent experience

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