Design Engineer V

Design Engineer V

Job Title: Design Engineer VReq: 19981-1Type: W2 Contract.Duration: 12 months with possible extension and conversion.Location: Sunnyvale, CA*Must be authorized to work in the US*Duties:Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floor plan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.Deliver physical design of an end-to-end IP or integration of ASIC/SoC design.Skills:Experience running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs.Experience in Block-level and Full-chip floor-planning and power grid planning.Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.Experience with Python, TCL, Perl programming.Education:Bachelor’s degree in Electrical Engineering or equivalent similar experience.10+ years experience in physical design.Understanding of RTL2GDS flow and design tape outs in 10nm/7nm or below process technologies.Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge.Experience working with EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus or Calibre.

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