Design Engineer IV – Digital Design Engineer/ASIC Engineer

Design Engineer IV – Digital Design Engineer/ASIC Engineer

Job Title: Design Engineer IVDuration: 12 months under W2Location: US-CA- Menlo ParkDigital Design Methodology and Release EngineerRESPONSIBILITIES• Run and maintain scripts for IP releases, triage issues, and make releases• Setup Spyglass Lint, CDC, and DFT flows, report status, triage issues, and drive closure• Setup Synopsys DC elaboration methodology flows, report status, triage issues, and drive closure• Support handoff and integration of blocks into larger SOC environments• Ability to document and communicate clearlyMINIMUM QUALIFICATIONS• 10-12 years of experience as a Digital Design Engineer• Experience in RTL coding, Spyglass Lint/CDC tools, Synthesis and LEC tools• Scripting experience (Python or similar languages)• BS Electrical Engineering/Computer Science or equivalent experiencePREFERRED QUALIFICATIONS• ASIC design experience• System Verilog OVM/UVM DV experience• GIT Version control• Masters Degree in EEOPTIONAL PLUS QUALIFICATION• Implement RTL using HLS and System Verilog• HLS coding using Catapult and Xilinx Vivado tools• Experience with Verilog code generators• Design of Computer Vision HardwareTop 3 Must have skills:Being able to run Spyglass tools: Experience in RTL coding, Spyglass Lint/CDC tools, Synthesis and LEC toolsWrite Python ScriptsGIT experiencePosted On: Thursday, May 13, 2021

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